The fabrication of semiconductor devices such as integrated circuits, memory cells, and the like, involve a series of manufacturing operations that are performed to define features on semiconductor wafers (“wafers”). The wafers include integrated circuit devices in the form of multi-level structures defined on a silicon substrate. At a substrate level, transistor devices with diffusion regions are formed. In subsequent levels, interconnect metallization lines are patterned and electrically connected to the transistor devices to define a desired integrated circuit device. Also, patterned conductive layers are insulated from other conductive layers by dielectric materials.
To build an integrated circuit, transistors are first created on the surface of the wafer. The wiring and insulating structures are then added as multiple thin-film layers through a series of manufacturing process steps. Typically, a first layer of dielectric (insulating) material is deposited on top of the formed transistors. Subsequent layers of metal (e.g., copper, aluminum, etc.) are formed on top of this base layer, etched to create the conductive lines that carry the electricity, and then filled with dielectric material to create the necessary insulators between the lines. The process used for producing copper lines is referred to as a dual Damascene process, where trenches are formed in a planar conformal dielectric layer, vias are formed in the trenches to open a contact to the underlying metal layer previously formed, and copper is deposited everywhere. Copper is then planarized (overburden removed), leaving copper in the vias and trenches only.
Although copper lines are typically comprised of a plasma vapor deposition (PVD) seed layer (i.e., PVD Cu) followed by an electroplated layer (i.e., ECP Cu), electroless chemistries are under consideration for use as a PVD Cu replacement, and even as an ECP Cu replacement. A process called electroless copper deposition can thus be used to build the copper conduction lines. During electroless copper deposition, electrons are transferred from a reducing agent to the copper ions resulting in the deposition of reduced copper onto the wafer surface. The formulation of the electroless copper plating solution is optimized to maximize the electron transfer process involving the copper ions.
Conventional formulations call for maintaining the electroless plating solution at a high alkaline pH (i.e., pH>9) to enhance the overall deposition rate. The limitations with using highly alkaline copper plating solutions for electroless copper deposition are non-compatibility with positive photoresist on the wafer surface, longer induction times, and decreased nucleation density due to an inhibition by hydroxylation of the copper interface (which occurs in neutral-to-alkaline environments). These are limitations that can be eliminated if the solution is maintained at an acidic pH environment (i.e., pH<7). One prominent limitation found with using acidic electroless copper plating solutions is that certain substrate surfaces, such as tantalum nitride (TaN), tend to get oxidized readily in an alkaline environment causing adhesion problems for the reduced copper resulting in blotchy plating on the TaN surfaces of the wafer. Efforts to counteract this limitation by seeding the TaN surfaces with various metals such as palladium and ruthenium have resulted in minimal levels of success primarily due to increase of the line resistance. With the growing interest in electroless plating solutions, is a concomitant interest in chambers capable of providing the environment for depositing the electroless plating solutions, especially with regard to solutions that tend to oxidize easily, e.g., cobalt plating solutions as well as copper plating solutions.
In view of the forgoing, there is a need for a chamber that enables the efficient use of improved formulations of copper plating solutions for use in electroless copper deposition processes, as well as other sensitive plating solutions.